Computer peripherals are typically connected to a computer system through one or more buses. Each bus typically supports a plurality of unique addresses, and each peripheral typically responds to one or more addresses or ranges of addresses within the plurality of addresses supported by each bus. Within the computer system, one or more CPUs are typically responsible for constructing and sending commands to each peripheral through these buses, though it will be readily apparent to one skilled in the art that such commands may also be generated by state logic implemented without the need of a CPU.
ATA hard disk devices are typical of the computer peripherals, which follow this model. Each device is connected to the computer through an ATA bus, sometimes also referred to as the IDE or EIDE bus, and each device responds to a unique address on the ATA bus. An ATA bus provides for two unique device addresses on each physical bus. The device responding to the first device address is referred to as the master and the device responding to the second device address is referred to as the slave. When only one device is connected to the ATA bus it is commonly, though not always, assigned the address corresponding to the master.
Computer systems incorporating ATA devices also generally incorporate an ATA controller. The ATA controller acts as an intermediary between the CPU or state logic responsible for generating each ATA command and the ATA devices. The ATA controller is typically connected directly to the ATA bus and also typically has a connection to a buffer management unit. The buffer management unit is typically responsible for directing data between the ATA controller and buffer memory. Buffer memory provides temporary storage for data exchanged with the ATA devices. Data in the buffer memory may be operated upon by a CPU or may be transferred elsewhere by way of one or more data interfaces also connected to the buffer memory controller. One skilled in the art will recognize that the buffer management unit described herein is a form of a DMA (Direct Memory Access) controller. DMA controllers are implemented in many forms, though all exhibit the property of being able to transfer data between memory and other devices or circuitry within a system and to do so independently of the CPU. To avoid confusion with other uses of the term DMA later in this specification, the DMA controller will be referred to as the buffer management unit.
The commands generated by the CPU or state logic for execution by the ATA devices are specified according to industry standards such as ATA-5 and ATA-6, which are examples of protocol specifications. As the needs for capacity, capability, and speed increase, new revisions of such industry standards are drafted and eventually adopted. New features added in such revisions are generally not supported by earlier implementations. In some cases, new features may be supported by modifying the CPU program code responsible for generating commands for the ATA devices. In other cases, the implementation of new features may require modifications to the hardware of state logic, of the ATA controller, or of the ATA devices. It is most common for this hardware to be implemented in custom ICs. Therefore, modifications to this hardware require redesigns to ICs, an expensive process which generally takes a minimum of three months and more commonly takes six to twelve months. The modification to ICs often further necessitates changes to the board designs incorporating these ICs and to the programs executed by the CPU responsible for generating commands. Lastly, there is often a reduction in shipments and a loss of revenue associated with the time spent modifying products to support new industry standards.
A specific example illustrates these effects. The ATA-6 specification adds new commands to allow the computer system to access the full capacity of ATA hard disk devices up to a capacity limit corresponding to 48-bit sector addresses wherein each sector is typically 512 bytes. This provides an effective addressable capacity of 281, 474, 976, 710, 655 sectors or approximately 144 petabytes. The earlier standards, up to and including the ATA-5 specification, provided commands capable of supporting a capacity limit corresponding to 28-bit sector addresses. The earlier standards therefore supported an effective addressable capacity of 268, 435, 455 sectors or approximately 137 gigabytes. When hard disks with capacities larger than 137 gigabytes started shipping, computer systems supporting the earlier standards up to and including the ATA-5 specification were unable to address the full capacity of the devices. For vendors of such high-capacity hard disks, this limited the effective market for the new hard disks. For computer system vendors, this created a support problem and a potential loss of business to competitors who could support the new ATA-6 standard.
One class of products for which the new ATA-6 standard presented such a problem is 1394-to-ATA device bridges. Such bridges permit standard ATA hard disks to be used as 1394 hard disks. 1394 is an IEEE standard describing a high-speed serial bus interface. IEEE-1394 is commonly referred to by the name given to it by Apple Computer known as FireWire. IEEE-1394 is also referred to by the name given to it by Sony known as i-Link.
Most 1394-to-ATA bridges are implemented using custom ICs, and at least one such widely used custom IC provides no built-in support for the new ATA-6 standard. This IC, the OXFW911 from Oxford Semiconductor, has hard-wired knowledge of all known ATA commands (op codes) up to and including those found in the ATA-5 specification. The OXFW911 therefore does not recognize the new ATA-6 commands. As such, the OXFW911 is unable to process ATA-6 commands correctly and fails to support the new ATA-6 standard. This means that 1394-to-ATA bridges using the OXFW911 are unable to work with drives supporting the ATA-6 standard. Although the OXFW911 may be used in a manual mode to send commands conforming to the ATA-6 standard, the OXFW911 will not recognize or interpret such manually sent commands. Consequently, the OXFW911 will not enable the automatic transfer of data between the ATA bus and the buffer management control unit for such manually sent commands. For example, the controller may not realize that data is to be received and may not turn on the OXFW911 buffer management control unit, thus preventing a high speed transfer of such data.
The OXFW911 is designed to recognize and interpret ATA commands, in part, so that it can determine the correct ATA transfer mode to use for each command. ATA transfer modes define the relationship and timing of specific ATA bus electrical signals used to exchange data across the ATA bus. Examples of ATA transfer modes are PIO (Programmed Input/Output) modes 0-4, DMA (Direct Memory Access) modes 0-2, and Ultra DMA modes 0-5. Note that the term DMA in the context of ATA transfer mode naming has no relationship to circuitry often associated with the buffer memory controller, which is also referred to as DMA.
As introduced in the preceding section, the most prevalent approach by which a computer system addresses peripheral devices is to assign unique addresses to each device. In such approaches, each device is connected to the computer system through one or more buses, each bus generally having a plurality of device addresses. Each device acts on or responds to messages sent to one or more addresses or ranges of addresses within this plurality of addresses available on each bus. The assignment of addresses to devices on each bus may be fixed at the time of design, fixed at the time of configuration, or may be dynamic, that is, assigned when the system runs. U.S. Pat. No. 4,249,240 to Barnich (1981), U.S. Pat. No. 4,796,025 to Farley et al. (1989), U.S. Pat. Nos. 4,910,655 (1990) and U.S. Pat. No. 4,918,598 (1990) to Ashkin et al., U.S. Pat. No. 5,107,256 to Ueno et al. (1992), and U.S. Pat. No. 5,191,655 to Sarkissian (1993) all refer to the use of unique device addresses for each device. U.S. Pat. No. 3,787,627 to Abramson et al. (1974) discusses the use of unique addresses for each device wherein said addresses are assigned dynamically.
A prevalent variation on the preceding approach is for a computer system to broadcast a message to other devices, including other computer systems or peripherals. In such approaches, one or more unique addresses on a bus are reserved as broadcast addresses. It is understood in such approaches that messages sent to such broadcast addresses are not necessarily intended for a specific recipient. Rather, the broadcast message will be interpreted by some or all devices on the bus and only those devices for which the broadcast message carries relevant information will act on or respond to the broadcast. U.S. Pat. No. 4,807,224 to Naron et al. (1989) refers to the use of such broadcasts.
The underlying assumption in the above-cited patents is that one or more devices will act on messages sent to one or more device addresses and that there will be a useful result as the byproduct of said action.